An integrated circuit (IC) may be subject to an Electrostatic Discharge (ESD) event in the manufacturing process, during assembly and testing, or in the system application. In conventional IC ESD protection schemes, special clamp circuits are often used to shunt ESD current between the power supply buses and thereby protect internal elements from damage. However, some ICs allow voltages higher than the internal power supply voltage for a specific process technology to be brought on board the IC. ESD protection for this high-voltage node can be achieved with a stacked, or series connected active MOSFET clamp configuration as a shunting circuit between the high-voltage node and a ground bus.
FIG. 1 illustrates in schematic diagram form a prior art ESD protection circuit 101. ESD protection circuit 101 includes an ESD bus labeled “ESD BUS”, an output buffer power supply bus labeled “VDD BUS”, a ground bus labeled “VSS BUS”, a trigger circuit 103, a shunting circuit 105, an input/output (I/O) pad 111, and diodes 113 and 115. It is assumed that during normal operation of the IC, the VDD BUS may be powered up to the maximum power supply voltage for a specific semiconductor process technology. This limit implies that no voltage higher than this maximum supply voltage may be applied across the gate oxide of any MOSFET (metal oxide semiconductor field effect transistor) in normal operation. In a typical high-voltage tolerant I/O application, the I/O pad may be driven externally to a voltage level up to twice as high as the maximum supply voltage. It is therefore assumed that, under normal operation, the ESD BUS may be maintained at the same high-voltage level since I/O pad 111 is coupled to the ESD BUS via diode 113. In an example IC application, the voltages on the VDD BUS and the ESD BUS may reach maximum voltages of 2.75 volts and 5.5 volts, respectively. Shunting circuit 105 includes cascoded NMOSFET rail clamp transistors 107 and 109. Trigger circuit 103 is coupled to the ESD BUS, the VDD BUS, and the VSS BUS. During normal operation of the IC, trigger circuit 103 provides a bias on the gate of transistor 107 equal to the voltage on the VDD BUS, and a bias on the gate of transistor 109 equal to the voltage on the VSS BUS, to insure that no voltage in excess of the maximum supply voltage is applied across the gate oxides of either transistor 107 or transistor 109. When an ESD event occurs, trigger circuit 103 provides a bias to the gates of both transistors 107 and 109 equal to the voltage on the ESD BUS local to these transistors. The I/O pad 111 is coupled to the ESD BUS and the VSS BUS via large ESD diodes 113 and 115, respectively. Diode 115 provides a high-current ESD path from the VSS BUS to I/O pad 111 in case of a negative ESD event on the I/O pad. When a positive ESD event with respect to VSS is applied to I/O pad 111, the intended high current path is from pad 111 through diode 113 to the ESD BUS and then through shunting circuit 105 to the VSS bus. During this ESD event, there may be a substantial IR voltage drop across diode 113 from I/O pad 111 to the ESD BUS, and along the ESD BUS between diode 113 and trigger circuit 103. Therefore, the gates of transistors 107 and 109 receive a relatively smaller bias voltage compared to the voltage at I/O pad 111, which effectively increases the on-resistance of transistors 107 and 109. To offset the higher on-resistance, large rail clamp transistors are typically used. However, the use of larger rail clamp transistors is undesirable because they require more chip area to implement. Therefore, there is a need for an ESD protection circuit that reduces the on-resistance of the ESD current path while minimizing the size of the ESD circuit.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.